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ZL9117M
TABLE 2. SMBus ADDRESS RESISTOR SELECTION
should be limited to a value that enables any device to assert the
bus to a voltage that ensures a logic 0 (typically 0.8V at the
R SA (k ? )
10
11
12.1
13.3
14.7
16.2
17.8
19.6
21.5
23.7
26.1, or connect to SGND
28.7, or Open
31.6, or connect to V25 or VR
34.8
38.3
42.2
46.4
51.1
56.2
61.9
68.1
75
82.5
90.9
100
SMBus ADDRESS
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
device monitoring point), given the pull-up voltage and the
pull-down current capability of the ZL9117M (nominally 4mA).
Phase Spreading
When multiple point-of-load converters share a common DC
input supply, it is desirable to adjust the clock phase offset of
each device such that not all devices start to switch
simultaneously. Setting each converter to start its switching cycle
at a different point in time, can dramatically reduce input
capacitance requirements and efficiency losses. Since the peak
current drawn from the input supply is effectively spread out over
a period of time, the peak current drawn at any given moment is
reduced, and the power losses proportional to the I RMS2 are
reduced dramatically.
To enable phase spreading, all converters must be synchronized
to the same switching clock. The phase offset of each device
may also be set to any value between 0° and 360° in 22.5°
increments via the I 2 C/SMBus interface. Refer to Application
Note AN2033 for further details.
Output Voltage Tracking
High performance systems place stringent demands on the order
in which the power supply voltages turn on. This is particularly
true when powering FPGAs, ASICs, and other advanced processor
devices that require multiple supply voltages to power a single
die. In most cases, the I/O interface operates at a higher voltage
than the core and therefore the core supply voltage must not
exceed the I/O supply voltage according to the manufacturers'
specifications. Voltage tracking protects these sensitive ICs by
limiting the differential voltage among multiple power supplies
during the power-up and power-down sequence.
The ZL9117M integrates a lossless tracking scheme that allows
its output to track a voltage that is applied to the VTRK pin with
no additional components required. The VTRK pin is an analog
input that, when tracking mode is enabled, and configures the
voltage applied to the VTRK pin to act as a reference for the
Digital-DC Bus
The Digital-DC Communications (DDC) bus is used to
communicate between Zilker Labs Digital-DC modules and
devices. This dedicated bus provides the communication channel
member device's output regulation.
Voltage tracking can be configured by PMBus only. An example is
shown in Figure 14.
SCL
between devices for features such as sequencing, fault
spreading, and current sharing. The DDC pin on all Digital-DC
devices in an application should be connected together. A pull-up
resistor is required on the DDC bus in order to guarantee the rise
time as shown in Equation 1:
SDA
SDA
SCL
VOUT
Vref
SDA
VTRK
SCL
VOUT
Vmem
Rise Time = R PU ? C LOAD ≈ 1 μ s
(EQ. 1)
ZL9117M
ZL9117M
where R PU is the DDC bus pull-up resistance and C LOAD is the
bus loading. The pull-up resistor may be tied to an external 3.3V
or 5V supply as long as this voltage is present prior to or during
device power-up. As rules of thumb, each device connected to the
DDC bus presents approximately 10pF of capacitive loading, and
each inch of FR4 PCB trace introduces approximately 2pF. The
ideal design uses a central pull-up resistor that is well-matched
to the total load capacitance. The minimum pull-up resistance
13
FIGURE 14. PMBUS TRACKING CONFIGURATION
The ZL9117M offers two modes of tracking: coincident and
ratiometric. Figures 15 and Figure 16 illustrate the output
voltage waveform for the two tracking modes.
FN7914.3
July 22, 2013
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